All Stratix
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S10F484I6
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 74/864闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX FPGA 10K LE 484-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 20
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 1057
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 10570
RAM 浣嶇附瑷�(j矛)锛� 920448
杓稿叆/杓稿嚭鏁�(sh霉)锛� 335
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FBGA锛�23x23锛�
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�绗�769闋�绗�770闋�绗�771闋�绗�772闋�绗�773闋�绗�774闋�绗�775闋�绗�776闋�绗�777闋�绗�778闋�绗�779闋�绗�780闋�绗�781闋�绗�782闋�绗�783闋�绗�784闋�绗�785闋�绗�786闋�绗�787闋�绗�788闋�绗�789闋�绗�790闋�绗�791闋�绗�792闋�绗�793闋�绗�794闋�绗�795闋�绗�796闋�绗�797闋�绗�798闋�绗�799闋�绗�800闋�绗�801闋�绗�802闋�绗�803闋�绗�804闋�绗�805闋�绗�806闋�绗�807闋�绗�808闋�绗�809闋�绗�810闋�绗�811闋�绗�812闋�绗�813闋�绗�814闋�绗�815闋�绗�816闋�绗�817闋�绗�818闋�绗�819闋�绗�820闋�绗�821闋�绗�822闋�绗�823闋�绗�824闋�绗�825闋�绗�826闋�绗�827闋�绗�828闋�绗�829闋�绗�830闋�绗�831闋�绗�832闋�绗�833闋�绗�834闋�绗�835闋�绗�836闋�绗�837闋�绗�838闋�绗�839闋�绗�840闋�绗�841闋�绗�842闋�绗�843闋�绗�844闋�绗�845闋�绗�846闋�绗�847闋�绗�848闋�绗�849闋�绗�850闋�绗�851闋�绗�852闋�绗�853闋�绗�854闋�绗�855闋�绗�856闋�绗�857闋�绗�858闋�绗�859闋�绗�860闋�绗�861闋�绗�862闋�绗�863闋�绗�864闋�
Altera Corporation
3鈥�1
July 2005
3. Configuration & Testing
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All Stratix devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be
performed either before or after, but not during configuration. Stratix
devices can also use the JTAG port for configuration together with either
the Quartus II software or hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc).
Stratix devices support IOE I/O standard setting reconfiguration through
the JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode through the
CONFIG_IO
instruction. You can use this ability for JTAG testing before
configuration when some of the Stratix pins drive or receive from other
devices on the board using voltage-referenced standards. Since the Stratix
device may not be configured before JTAG testing, the I/O pins may not
be configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows you
to fully test the I/O connection to other devices.
The enhanced PLL reconfiguration bits are part of the JTAG chain before
configuration and after power-up. After device configuration, the PLL
reconfiguration bits are not part of the JTAG chain.
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The
TDO
pin voltage is determined by the VCCIO of the bank where it resides.
The VCCSEL pin selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Stratix devices also use the JTAG port to monitor the logic operation of the
device with the SignalTap II embedded logic analyzer. Stratix devices
support the JTAG instructions shown in Table 3鈥�1.
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JTAG user
code. If selected, the checksum is automatically loaded to the USERCODE
register. In the Settings dialog box in the Assignments menu, click Device
& Pin Options
, then General, and then turn on the Auto Usercode
option.
S51003-1.3
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
IDT7025S15PF IC SRAM 128KBIT 15NS 100TQFP
EP1S10F484C5 IC STRATIX FPGA 10K LE 484-FBGA
EP1S10F780I6N IC STRATIX FPGA 10K LE 780-FBGA
EP1S10F780C5N IC STRATIX FPGA 10K LE 780-FBGA
ACM44DRAH CONN EDGECARD 88POS .156 R/A
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EP1S10F484I6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 335 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F672C6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 345 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F672C6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 345 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F672C7 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 345 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F672C7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 345 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256