參數(shù)資料
型號(hào)： EP1K50TC144-2P
元件分類(lèi)： 數(shù)字電位計(jì)
英文描述： Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 6-SC-70 T&R
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）
文件頁(yè)數(shù)： 31/86頁(yè)
文件大?。?/td> 1263K
代理商： EP1K50TC144-2P
Altera Corporation
37
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the Altera
software, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 19 shows the incoming and generated clock
specifications.
Figure 19. Specications for the Incoming & Generated Clocks
Note:
(1)
The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock
period.
Input
Clock
ClockLock
Generated
Clock
tCLK1
tINDUTY
tI+ tCLKDEV
tR
tF
tO
tI+ tINCLKSTB
tO
tO tJITTER
tO+ tJITTER
tOUTDUTY
相關(guān)PDF資料
PDF描述
EP1K50TC144-2X Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R
EP1K50TC144-3F Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R
EP1K50TI144-1DX Field Programmable Gate Array (FPGA)
EP1K50FC256-1DX Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
EP1K50FC256-1F Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50TC144-2X 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50TC144-3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 360 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K50TC144-3 制造商:Altera Corporation 功能描述:ACEX 1K PLD 1K50 TQFP144 3.3V
EP1K50TC144-3F 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50TC144-3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 360 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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