參數(shù)資料
型號(hào)： EP1K50QI208-1DX
英文描述： 250mA Single LDO with Low IQ, Low Noise and High PSRR LDO; Temperature Range: -40°C to 85°C; Package: 6-uTDFN T&R
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 45/86頁(yè)
文件大?。?/td> 1263K
代理商： EP1K50QI208-1DX
Altera Corporation
5
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Table 5 shows ACEX 1K device performance for more complex designs.
These designs are available as Altera MegaCoreTM functions.
Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cables.
After an ACEX 1K device has been configured, it can be reconfigured in-
circuit by resetting the device and loading new data. Because
reconfiguration requires less than 40 ms, real-time changes can be made
during system operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it by writing to a virtual
memory location, simplifying device reconfiguration.
Table 5. ACEX 1K Device Performance for Complex Designs
Application
LEs
Used
Performance
Speed Grade
Units
-1
-2
-3
16-bit, 8-tap parallel finite impulse response (FIR)
filter
597
192
156
116
MSPS
8-bit, 512-point Fast Fourier transform (FFT)
function
1,854
23.4
28.7
38.9
s
113
92
68
MHz
a16450
universal asynchronous
receiver/transmitter (UART)
342
36
28
20.5
MHz
相關(guān)PDF資料
PDF描述
EP1K50QI208-1F Field Programmable Gate Array (FPGA)
EP1K50QI208-1P Field Programmable Gate Array (FPGA)
EP1K50QI208-1X Field Programmable Gate Array (FPGA)
EP1K50QI208-2DX Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 5-SC-70 T&R
EP1K50QI208-2F Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50QI208-1F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-1P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K50QI208-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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