參數(shù)資料
型號: EP1K50FI484-1P
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 82/86頁
文件大小: 1263K
代理商: EP1K50FI484-1P
Altera Corporation
83
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Figure 31. ACEX 1K ICCACTIVE vs. Operating Frequency
Conguration &
Operation
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as VCC rises, the device initiates a
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50
s.
1
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
0
Frequency (MHz)
300
200
100
50
100
EP1K100
ICC Supply
Current (mA)
0
Frequency (MHz)
ICC Supply
Current (mA)
100
80
60
40
20
50
100
EP1K30
0
Frequency (MHz)
ICC Supply
Current (mA)
200
150
100
50
100
EP1K50
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50FI484-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述:
EP1K50FI484-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)