參數(shù)資料
型號: EP1K50FI484-1F
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 2/86頁
文件大?。?/td> 1263K
代理商: EP1K50FI484-1F
10
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Notes:
(1)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2)
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3. The
ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
Column Interconnect
EAB Local
Interconnect (2)
Dedicated Clocks
24
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
256
× 16
512
× 8
1,024
× 4
2,048
× 2
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
4, 8, 16, 32
outclocken
inclocken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Row Interconnect
4, 8
Dedicated Inputs &
Global Signals
相關(guān)PDF資料
PDF描述
EP1K50FI484-1P Field Programmable Gate Array (FPGA)
EP1K50FI484-1X Field Programmable Gate Array (FPGA)
EP1K50FI484-2DX Field Programmable Gate Array (FPGA)
EP1K50FI484-2F Field Programmable Gate Array (FPGA)
EP1K50FI484-2P Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50FI484-1P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述:
EP1K50FI484-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)