鍨嬭櫉(h脿o)锛� | EP1K50FC484-1N |
寤犲晢锛� | Altera |
鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 30/86闋�(y猫) |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC ACEX 1K FPGA 50K 484-FBGA |
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
绯诲垪锛� | ACEX-1K® |
LAB/CLB鏁�(sh霉)锛� | 360 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 2880 |
RAM 浣嶇附瑷�(j矛)锛� | 40960 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 249 |
闁€鏁�(sh霉)锛� | 199000 |
闆绘簮闆诲锛� | 2.375 V ~ 2.625 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 70°C |
灏佽/澶栨锛� | 484-BGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 484-FBGA锛�23x23锛� |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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EP1K50FC484-1 | IC ACEX 1K FPGA 50K 484-FBGA |
HMC43DRXN | CONN EDGECARD 86POS DIP .100 SLD |
HMC43DRXH | CONN EDGECARD 86POS DIP .100 SLD |
HMC49DRTS | CONN EDGECARD 98POS DIP .100 SLD |
HMC49DRES | CONN EDGECARD 98POS .100 EYELET |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EP1K50FC484-1P | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA) |
EP1K50FC484-1X | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA) |
EP1K50FC484-2 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP1K50FC484-2DX | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA) |
EP1K50FC484-2F | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA) |