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    參數(shù)資料
    

    


    


    
型號：
EP1K30FC256-2

    

    
廠商：
Altera

    

    
文件頁數(shù)：
18/86頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC ACEX 1K FPGA 30K 256-FBGA

    

    
產(chǎn)品培訓(xùn)模塊：
Three Reasons to Use FPGA's in Industrial Designs
    		

    

    
標準包裝：
90

    

    
系列：
ACEX-1K®

    

    
LAB/CLB數(shù)：
216
    		

    

    
邏輯元件/單元數(shù)：
1728
    		

    

    
RAM 位總計：
24576
    		

    

    
輸入/輸出數(shù)：
171
    		

    

    
門數(shù)：
119000
    		

    

    
電源電壓：
2.375 V ~ 2.625 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
256-BGA
    		

    

    
供應(yīng)商設(shè)備封裝：
256-FBGA（17x17）
    		

    

    
產(chǎn)品目錄頁面：
602 (CN2011-ZH PDF)
    		

    

    
其它名稱：
544-1831
    EP1K30FC256-2-ND
    		

    

    

    

	
    
    
    

    
    
	
    Altera Corporation
    25
    ACEX 1K Programmable Logic Device Family Data Sheet
    D
    e
    ve
    lo
    pm
    e
    n
    t
    13
    To
    o
    ls
    Asynchronous Clear
    The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
    mode, the preset signal is tied to VCC to deactivate it.
    Asynchronous Preset
    An asynchronous preset is implemented as an asynchronous load, or with
    an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
    asynchronously loads a one into the register. Alternatively, the Altera
    software can provide preset control by using the clear and inverting the
    register’s input and output. Inversion control is available for the inputs to
    both LEs and IOEs. Therefore, if a register is preset by only one of the two
    LABCTRL
    signals, the DATA3 input is not needed and can be used for one
    of the LE operating modes.
    Asynchronous Preset & Clear
    When implementing asynchronous clear and preset, LABCTRL1 controls
    the preset, and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
    asserting LABCTRL1 asynchronously loads a one into the register,
    effectively presetting the register. Asserting LABCTRL2 clears the register.
    Asynchronous Load with Clear
    When implementing an asynchronous load in conjunction with the clear,
    LABCTRL1
    implements the asynchronous load of DATA3 by controlling
    the register preset and clear. LABCTRL2 implements the clear by
    controlling the register clear; LABCTRL2 does not have to feed the preset
    circuits.
    Asynchronous Load with Preset
    When implementing an asynchronous load in conjunction with preset, the
    Altera software provides preset control by using the clear and inverting
    the input and output of the register. Asserting LABCTRL2 presets the
    register, while asserting LABCTRL1 loads the register. The Altera software
    inverts the signal that drives DATA3 to account for the inversion of the
    register’s output.
    Asynchronous Load without Preset or Clear
    When implementing an asynchronous load without preset or clear,
    LABCTRL1
    implements the asynchronous load of DATA3 by controlling
    the register preset and clear.
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
EP1K30FC256-2N
功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 216 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP1K30FC256-3
功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 216 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP1K30FC256-3N
功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 216 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP1K30FI256-2
功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 216 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP1K30FI256-2N
功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 216 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
    
    
    
	
    	
    
    
     
     
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