f For more information on the configu" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1K10TC100-1N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 56/86闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ACEX 1K FPGA 10K 100-TQFP
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 270
绯诲垪锛� ACEX-1K®
LAB/CLB鏁�(sh霉)锛� 72
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 576
RAM 浣嶇附瑷堬細 12288
杓稿叆/杓稿嚭鏁�(sh霉)锛� 66
闁€鏁�(sh霉)锛� 56000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-TQFP
渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
6
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
f For more information on the configuration of ACEX 1K devices, see the
following documents:
ACEX 1K devices are supported by Altera development systems, which
are integrated packages that offer schematic, text (including AHDL), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains, which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development system includes DesignWare
functions that are optimized for the ACEX 1K device architecture.
The Altera development systems run on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations.
f For more information, see the MAX+PLUS II Programmable Logic
Functional
Description
Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
鐩搁棞(gu膩n)PDF璩囨枡
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EP1K10TC100-2 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1K10TC100-2N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1K10TC100-3 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
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