-1 speed grade devices are compliant with PCI Local" />
參數(shù)資料
型號： EP1K10TC100-1
廠商： Altera
文件頁數(shù)： 12/86頁
文件大小： 0K
描述： IC ACEX 1K FPGA 10K 100-TQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 270
系列： ACEX-1K®
LAB/CLB數(shù)： 72
邏輯元件/單元數(shù)： 576
RAM 位總計： 12288
輸入/輸出數(shù)： 66
門數(shù)： 56000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
2
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
–
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2
for 5.0-V operation
–
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
–
Operate with a 2.5-V internal supply voltage
–
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
–
ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
–
Built-in, low-skew clock distribution trees
–100% functional testing of all devices; test vectors or scan chains
are not required
–
Pull-up on I/O pins before and during configuration
■
Flexible interconnect
–FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Tri-state emulation that implements internal tri-state buses
–
Up to six global clock signals and four global clear signals
■
Powerful I/O pins
–
Individual tri-state output enable control for each pin
–
Open-drain option on each I/O pin
–
Programmable output slew-rate control to reduce switching
noise
–Clamp to VCCIO user-selectable on a pin-by-pin basis
–
Supports hot-socketing
相關(guān)PDF資料
PDF描述
HSM43DRYS CONN EDGECARD 86POS DIP .156 SLD
EP4CE6E22I8L IC CYCLONE IV FPGA 6K 144EQFP
A3PN250-1VQG100I IC FPGA NANO 250K GATES 100-VQFP
A3PN250-Z1VQG100I IC FPGA NANO 250K GATES 100-VQFP
HMM43DRYS CONN EDGECARD 86POS DIP .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K10TC100-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC100-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC100-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC100-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC100-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*