Notes: (1) Al" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1K10QC208-1
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 2/86闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ACEX 1K FPGA 10K 208-PQFP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 144
绯诲垪锛� ACEX-1K®
LAB/CLB鏁�(sh霉)锛� 72
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 576
RAM 浣嶇附瑷堬細 12288
杓稿叆/杓稿嚭鏁�(sh霉)锛� 120
闁€鏁�(sh霉)锛� 56000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
10
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Notes:
(1)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2)
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3. The
ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
Column Interconnect
EAB Local
Interconnect (2)
Dedicated Clocks
24
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
256
脳 16
512
脳 8
1,024
脳 4
2,048
脳 2
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
4, 8, 16, 32
outclocken
inclocken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Row Interconnect
4, 8
Dedicated Inputs &
Global Signals
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EP1K10QC208-1N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - ACEX 1K 72 LABs 120 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
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