Notes: (1) EP1K10, EP1K30, and EP1K50 devices h" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EP1K10FC256-2
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 6/86闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ACEX 1K FPGA 10K 256-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ACEX-1K®
LAB/CLB鏁�(sh霉)锛� 72
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 576
RAM 浣嶇附瑷�(j矛)锛� 12288
杓稿叆/杓稿嚭鏁�(sh霉)锛� 136
闁€鏁�(sh霉)锛� 56000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 256-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FBGA锛�17x17锛�
14
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 7. ACEX 1K LAB
Notes:
(1)
EP1K10, EP1K30, and EP1K50 devices have 22 inputs to the LAB local interconnect channel from the row; EP1K100
devices have 26.
(2)
EP1K10, EP1K30, and EP1K50 devices have 30 LAB local interconnect channels; EP1K100 devices have 34.
2
8
Carry-In &
Cascade-In
LE1
LE8
LE2
LE3
LE4
LE5
LE6
LE7
Column
Interconnect
Row Interconnect
(1)
LAB Local
Interconnect (2)
Column-to-Row
Interconnect
Carry-Out &
Cascade-Out
16
24
LAB Control
Signals
See Figure 13
for details.
6
Dedicated Inputs &
Global Signals
16
6
8
4
2
8
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
EP1K10FC256-2N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1K10FC256-3 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1K10FC256-3N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1K10FI256-2 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1K10FI256-2N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256