參數(shù)資料
型號： EP1K10
廠商： Electronic Theatre Controls, Inc.
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 1/86頁
文件大?。?/td> 992K
代理商： EP1K10
Altera Corporation
1
ACEX 1K
Programmable Logic Device Family
September 2001, ver. 3.3
Data Sheet
A-DS-ACEX-3.3
D
13
T
Features...
I
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
–
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
–
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
–
Logic array for general logic functions
High density
–
10,000 to 100,000 typical gates (see
Table 1
)
–
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
–
Cost-optimized process
–
Low cost solution for high-performance communications
applications
System-level features
–
MultiVolt
TM
I/ O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
–
Low power consumption
–
Bidirectional I/ O performance (setup time [
t
SU
] and clock-to-
output delay [
t
CO
]) up to 250 MHz
–
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG)
PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 MHz or 66 MHz
I
I
I
Table 1. ACEX
TM
1K Device Features
Feature
EP1K10
EP1K30
EP1K50
EP1K100
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
10,000
56,000
576
3
12,288
136
30,000
119,000
1,728
6
24,576
171
50,000
199,000
2,880
10
40,960
249
100,000
257,000
4,992
12
49,152
333
相關(guān)PDF資料
PDF描述
EP1K100 Programmable Logic Device Family
EP1K30 Programmable Logic Device Family
EP1K50 Programmable Logic Device Family
EP1S60B1508C5ES Stratix Device Family Data Sheet
EP1S10B1508C6ES Stratix Device Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Logic Device Family
EP1K100FC256-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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