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參數(shù)資料
| 型號(hào)： | DS1254Y |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PBGA168 |
| 封裝： | BGA-168 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 161K |
| 代理商： | DS1254Y |
DS1254
14 of 17
NOTES:
1. Voltage referenced to ground.
2. These parameters are sampled with a 50 pF load and are not 100% tested.
3. BW is an open drain output and, as such, cannot source current. An external pullup resistor should be
connected to this pin for proper operation. BW can sink 10 mA.
4. The DS3800 Battery Cap is a one time use part, but can be removed and replaced. By Design,
removal of a DS3800 will mechanically damage the Battery Cap which eliminates the accidental use
of a previously attached and possibly low capacity Battery Cap.
5. tWP specified as the logical AND of CE and WE , tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
6. TAH1, tDH1 are measured from WE going high..
7. TAH2, tDH2 are measured from CE going high.
8. tDS is measured from the earlier of CE or WE going high.
9.
WE
is high for a read cycle.
10. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
11. If the CE low transition occurs simultaneously with or later than the WE low transition in a write
enable controlled write cycle, the output buffers remain in a high impedance state during this period.
12. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
13. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
14. In a power down condition, the voltage on any pin may not exceed the voltage on VCC.
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