參數(shù)資料
型號： EN29F040-70P
廠商： Electronic Theatre Controls, Inc.
英文描述： 4 Megabit (512K x 8-bit) Flash Memory
中文描述： 4兆位（為512k × 8位）閃存
文件頁數(shù)： 11/32頁
文件大小： 223K
代理商： EN29F040-70P
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
11
EN29F040
Rev. D, Issue Date: 2001/07/05
WRITE OPERATION STATUS
DQ7
DATA
Polling
The EN29F040 provides
DATA
Polling on DQ7 to indicate to the host system the status of the
embedded operations. The
DATA
Polling feature is active during the Byte Programming, Sector
Erase, Chip Erase, and Erase Suspend. (See Table 6)
When the Byte Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the Byte Programming, an
attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,
DATA
polling is valid after the rising edge of the fourth
WE
or
CE
pulse in the four-cycle sequence.
When the embedded Erase is in progress, an attempt
to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the
DATA
polling is valid after the rising edge of the sixth
W E
or
CE
pulse in the six-cycle sequence. For Sector Erase,
DATA
polling is valid after the last
rising edge of the sector erase
W E
or
CE
pulse.
DATA
Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise,
DATA
polling may give an inaccurate result if the address
used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (
OE
) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid
data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for
DATA
Polling (DQ7) is shown on Flowchart 5. The
DATA
Polling (DQ7) timing
diagram is shown in Figure 8.
DQ6
Toggle Bit I
The EN29F040 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling
OE
or
CE
) will result in DQ6 toggling between “zero” and “one”. Once
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth
WE
pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid
after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the
last rising edge of the Sector Erase
W E
pulse. The Toggle Bit is also active during the sector erase
time-out window.
相關(guān)PDF資料
PDF描述
EN29F040-70PI 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-70T 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-70TI 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-90J 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-90JI 4 Megabit (512K x 8-bit) Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EN29F040-70PI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-70T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-70TI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-90J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-90JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
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