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參數(shù)資料
| 型號： | EM512D16 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16 bit Ultra-Low Power Asynchronous Static RAM |
| 中文描述： | 為512k × 16位超低功耗異步靜態(tài)RAM |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 54K |
| 代理商： | EM512D16 |
NanoAmp Solutions, Inc.
4
Stock No. 23144-B 3/01
Advance - Subject to Change Without Notice
EM512D16
Advance Information
TABLE 6: Timing Test Conditions
TABLE 7: Timing
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
5ns
0.5 V
CC
-40 to +85
o
C
Input Rise and Fall Time
Input and Output Timing Reference Levels
Operating Temperature
Item
Symbol
V
CCQ =
2.3 - 3.6 V
V
CCQ =
2.7 - 3.6 V
Units
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
t
AA
t
AAW
t
CO
t
OE
t
LB
, t
UB
t
LZ
t
OLZ
t
LBZ
, t
UBZ
t
HZ
t
OHZ
t
LBHZ
, t
UBHZ
t
OH
t
WC
t
CW
t
AW
t
LBW
, t
UBW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
85
70
ns
ns
Address Access Time (Random Access)
85
70
Address Access Time (Word Mode)
85
70
ns
Chip Enable to Valid Output
85
70
ns
Output Enable to Valid Output
30
25
ns
Byte Select to Valid Output
85
70
ns
Chip Enable to Low-Z output
10
10
ns
Output Enable to Low-Z Output
Byte Select to Low-Z Output
5
10
5
10
ns
ns
Chip Disable to High-Z Output
0
20
0
20
ns
Output Disable to High-Z Output
0
20
0
20
ns
Byte Select Disable to High-Z Output
0
20
0
20
ns
Output Hold from Address Change
10
10
ns
Write Cycle Time
85
70
ns
Chip Enable to End of Write
50
50
ns
Address Valid to End of Write
Byte Select to End of Write
40
50
40
50
ns
ns
Write Pulse Width
40
40
ns
Address Setup Time
0
0
ns
Write Recovery Time
0
0
ns
Write to High-Z Output
20
20
ns
Data to Write Time Overlap
40
40
ns
ns
Data Hold from Write Time
End Write to Low-Z Output
0
5
0
5
ns
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