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參數(shù)資料
| 型號(hào)： | EM48AM3284LBA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512Mb (4M】4Bank】32) Synchronous DRAM |
| 中文描述： | 的512Mb（4分】4Bank】32）同步DRAM |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大小： | 231K |
| 代理商： | EM48AM3284LBA |
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eorex
EM48AM3284LBA
Jul. 2006
www.eorex.com
15/17
4. Operative Command Table (Continued)
(Note 7)
Current
State
/CS
/R /C /W
Addr.
Command
Action
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
L
L
X
H
H
H
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
X
H
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
X
X
X
DESL
NOP
BST
Nop
→
Enter row active after t
DPL
Nop
→
Enter row active after t
DPL
Nop
→
Enter row active after t
DPL
Start read, Determine AP
New write, Determine AP
(Note 14)
ILLEGAL
(Note 9)
ILLEGAL
(Note 9)
ILLEGAL
ILLEGAL
Nop
→
Enter pre-charge after t
DPL
Nop
→
Enter pre-charge after t
DPL
Nop
→
Enter pre-charge after t
DPL
ILLEGAL
(Note 9, 14)
ILLEGAL
(Note 9)
ILLEGAL
(Note 9)
ILLEGAL
ILLEGAL
ILLEGAL
Nop
→
Enter idle after t
RC
Nop
→
Enter idle after t
RC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
X
X
X
X
X
X
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRIT
ACT/PRE/PALL/
REF/SELF/MRS
Write
Recovering
Write
Recovering
with AP
Refreshing
Mode
Register
Accessing
L
L
X
X
X
ILLEGAL
Remark
H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Note 7:
All entries assume that CKE was active (High level) during the preceding clock cycle.
Note 8:
If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
Note 9:
Illegal to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
Note 10:
If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
Note 11:
Illegal if t
RCD
is not satisfied.
Note 12:
Illegal if t
RAS
is not satisfied.
Note 13:
Must satisfy burst interrupt condition.
Note 14:
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Note 15:
Must mask preceding data which don't satisfy t
DPL
.
Note 16:
Illegal if t
RRD
is not satisfied.
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