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參數(shù)資料
| 型號： | EM424M824VTB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16Mb ( 2Banks ) Synchronous DRAM |
| 中文描述： | 16兆（2Banks）同步DRAM |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 833K |
| 代理商： | EM424M824VTB |
Rev.01
16Mb SDRAM
17/18
Parameter
Symbol
Units
-6/6I/6L
-7/7L
Min.
Min.
-5
Min.
Max.
Max.
Max.
Clock cycle time
Access time from CLK
Data-out hold time
Data-out high impedance time
CLK high level width
CLK low level width
Input setup time
Input hold time
ACTIVE to ACTIVE command period
ACTIVE to PRECHARGE command period
PRECHARGE to ACTIVE command period
ACTIVE to READ/WRITE delay time
ACTIVE(one) to ACTIVE(another) command
READ/WRITE command to READ/WRITE
command
Data-in to PRECHARGE command
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
t
CK
t
AC
t
CH
t
CL
t
OH
t
HZ
t
LZ
t
IS
t
IH
t
RC
t
RAS
t
RP
t
RCD
t
RRD
t
CCD
7
7.5
5.5
5.5
1.5
2
5
4.5
1.5
1.5
1.5
5
0
1.5
54
40
18
14
10
1
100k
6
2
2
0
1.5
60
42
18
18
12
100k
6
5
7
8
5.5
5
2.75
22
2
2
7
1
1
100k
2
65
45
18
20
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
t
DPL
2
2
2
CLK
Data-out to high impedance from
PRECHARGE command
Data-in to BURST stop command
Refresh time(2,048 cycle)
CL = 3
CL = 2
t
BDL
t
ROH
t
REF
1
3
32
1
3
32
1
3
2
32
CLK
CLK
CLK
ms
Data-out low impedance time
Operating AC Characteristics
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I)
Notes
2
2
2
2
2
＊
All voltages referenced to Vss.
Note :
1. t
HZ
defines the time at which the output achieve the open circuit
condition and is not referenced to output voltage levels.
2. These parameters account for the number of clock cycles and
depend on the operating frequency of the clock, as follows :
The number of clock cycles = Specified value of timing/clock
period
(Count fractions as a whole number)
2
1
1
1.5
1
1
2
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