FN7506.0 February 14, 2005 Description of Operation and Application Information Product Description The EL5624A is fabricat" />
參數(shù)資料
型號(hào): EL5624AIREZ
廠商: Intersil
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 0K
描述: IC BUFFER 6-CHANNEL 20-HTSSOP
標(biāo)準(zhǔn)包裝: 74
應(yīng)用: TFT-LCD 面板:伽瑪緩沖器,VCOM 驅(qū)動(dòng)器
輸出類型: 滿擺幅
電路數(shù): 6
-3db帶寬: 12MHz
轉(zhuǎn)換速率: 15 V/µs
電流 - 電源: 8.5mA
電流 - 輸出 / 通道: 140mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 16.5 V,±2.25 V ~ 8.25 V
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 20-TSSOP-EP
包裝: 管件
7
FN7506.0
February 14, 2005
Description of Operation and Application
Information
Product Description
The EL5624A is fabricated using a high voltage CMOS
process. It exhibits rail to rail input and output capability and
has very low power consumption. When driving a load of
10K and 12pF, this buffer has a -3dB bandwidth of 12MHz
and exhibit 18V/s slew rate. The VCOM amplifier has a
-3dB bandwidth of 35MHz and exhibit 70V/s slew rate.
Input, Output, and Supply Voltage Range
The EL5624A is specified with a single nominal supply
voltage from 5V to 15V or a split supply with its total range
from 5V to 15V. Correct operation is guaranteed for a supply
range from 4.5V to 16.5V.
The input common-mode voltage range of the EL5624A
extends 500mV beyond the supply rails. The output swings
of the buffers and VCOM amplifier typically extend to within
100mV of the positive and negative supply rails with load
currents of 5mA. Decreasing load currents will extend the
output voltage even closer to each supply rails.
Output Phase Reversal
The EL5624A is immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V.
Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diode placed in the input stage of the device begin
to conduct and overvoltage damage could occur.
FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
100
60
-60
-100
20
-20
1K
100M
10K
100K
1M
10M
FREQUENCY (Hz)
GA
IN
(
d
B)
PHASE
)
150
-150
50
-50
PHASE
GAIN
VS=±7.5V
RL=1k
CL=1.5pF
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.6
0.4
0.3
0.2
0.1
0
255075
100
150
AMBIENT TEMPERATURE (°C)
POWER
DISS
IP
AT
ION
(W)
85
0.8
0.5
0.7
125
800mW
θ
JA =
125
°C
/W
HT
SS
OP
20
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - HTSSOP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.5
3
2.5
1.5
1
0.5
0
255075
100
150
AMBIENT TEMPERATURE (°C)
PO
WER
D
ISS
IP
A
T
IO
N
(W)
2.857W
θ
JA =
35
°C
/W
HT
SS
OP
20
125
85
2
EL5624A
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