參數(shù)資料
型號: EL5420TISZ-T13
廠商: Intersil
文件頁數(shù): 6/17頁
文件大?。?/td> 0K
描述: IC OPAMP GP RR 12MHZ QD 14SOIC
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 電壓反饋
電路數(shù): 4
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 12 V/µs
增益帶寬積: 8MHz
-3db帶寬: 12MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 4000µV
電流 - 電源: 500µA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 19 V,±2.25 V ~ 9.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 帶卷 (TR)
14
FN6838.0
September 25, 2009
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5420T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly
recommended, trace lengths should be as short as possible
and the power supply pins must be well bypassed to reduce
any risk of oscillation.
For normal single supply operation (the VS- pin is connected
to ground) a 4.7F capacitor should be placed from VS+ to
ground, then a parallel 0.1F capacitor should be connected
as close to the amplifier as possible. One 4.7F capacitor
may be used for multiple devices. For dual supply operation
the same capacitor combination should be placed at each
supply pin to ground.
For the QFN package, with exposed thermal pad, the pad
should be connected to the lowest potential, VS-, to optimize
thermal and operating performance. PCB vias should be
placed below the device’s exposed thermal pad to transfer
heat to the VS- plane and away from the device.
Revision History
DATE
REVISION
CHANGE
9/25/09
FN6838.0
Initial Release
EL5420T
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