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參數(shù)資料
| 型號： | EL4585CS-T13 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GENLOCK HORZ 8FSC 16-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 鎖相環(huán)路（PLL） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 36MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
1
FN7175.4
EL4585
Horizontal Genlock, 8FSC
The EL4585 is a PLL (Phase Lock Loop) sub-system,
designed for video applications and also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS-compatible pixel clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 sync separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing such as VTR head switching. The lock detector output
indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards by external
selection of three control pins. These four ratios have been
selected for common video applications including 8FSC,
6FSC, 27MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
4FSC, 3FSC, 13.5MHz (CCIR 601 format) etc., use the
EL4584, which does not have the additional divide-by-two
stage of the EL4585.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
Features
36MHz, general purpose PLL
8FSC timing (use the EL4584 for 4FSC)
Compatible with EL4583 sync separator
VCXO, Xtal, or LC tank oscillator
< 2ns jitter (VCXO)
User-controlled PLL capture and lock
Compatible with NTSC and PAL TV formats
8 pre-programmed popular TV scan rate clock divisors
Single 5V, low current operation
Pb-Free Available (RoHS Compliant)
Applications
Pixel clock regeneration
Video compression engine (MPEG) clock generator
Video capture or digitization
PIP (Picture in Picture) timing generator
Text or graphics overlay timing
Demo Board
A demo PCB is available for this product.
FREQUENCIES AND DIVISORS
FUNCTION
6FSC
(Note 1)
CCIR 601
(Note 2)
SQUARE
(Note 3)
8FSC
Divisor (Note 4)
1702
1728
1888
2270
PAL FOSC (MHz)
26.602
27.0
29.5
35.468
Divisor (Note 4)
1364
1716
1560
1820
NTSC FOSC (MHz)
21.476
27.0
24.546
28.636
NOTES:
1. 6FSC frequencies do not yield integer divisors.
2. CCIR 601 divisors yield 1440 pixels in the active portion of each
line for NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL.
4. Divisor does not include ÷ 2 block.
Ordering Information
PART
NUMBER
PART
MARKING
PACKAGE
PKG.
DWG. #
EL4585CN
16 Ld PDIP
E16.3
EL4585CS
16 Ld SOIC
MDP0027
EL4585CS-T7*
EL4585CS
16 Ld SOIC
MDP0027
EL4585CS-T13*
EL4585CS
16 Ld SOIC
MDP0027
EL4585CSZ
(Note 5)
EL4585CSZ
16 Ld SOIC
(Pb-free)
MDP0027
EL4585CSZ-T7*
(Note 5)
EL4585CSZ
16 Ld SOIC
(Pb-free)
MDP0027
EL4585CSZ-T13*
(Note 5)
EL4585CSZ
16 Ld SOIC
(Pb-free)
MDP0027
NOTES:
5. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet
or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. For 3FSC and 4FSC clock frequency operation, see EL4584
datasheet.
Data Sheet
September 3, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EL4585CS-T7 | 功能描述:IC PLL VIDEO GP 36MHZ 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| EL4585CSZ | 功能描述:鎖相環(huán) - PLL EL4585CSZ HORIZONTAL GENLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL4585CSZ-T13 | 功能描述:鎖相環(huán) - PLL EL4585CSZ HORIZONTAL GENLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL4585CSZ-T7 | 功能描述:鎖相環(huán) - PLL EL4585CSZ HORIZONTAL GENLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL-484ET | 功能描述:標準LED-通孔 Orange Translucent 625nm 4mcd RoHS:否 制造商:Vishay Semiconductors 照明顏色:Red 光強度:0.7 mcd 波長/色溫:615 nm 顯示角:45 deg 透鏡顏色/類型:Clear, Non-Diffused 正向電流:70 mA 正向電壓:1.83 V to 3.03 V LED 大小:2 mm 系列: 封裝:Tube |
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