VOUT = ((R2+R1)/R1)" />
參數(shù)資料
型號: EL2142CS-T13
廠商: Intersil
文件頁數(shù): 4/6頁
文件大?。?/td> 0K
描述: IC LINE RECEIVER DIFF 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 差分
電路數(shù): 1
轉(zhuǎn)換速率: 400 V/µs
增益帶寬積: 200MHz
-3db帶寬: 150MHz
電流 - 輸入偏壓: 6µA
電壓 - 輸入偏移: 10000µV
電流 - 電源: 11mA
電流 - 輸出 / 通道: 60mA
電壓 - 電源,單路/雙路(±): 6 V ~ 12.6 V,±3 V ~ 6.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
4
FN7049.1
February 11, 2005
Applications Information
Gain Equation
VOUT = ((R2+R1)/R1) x (VIN-VINB+VREF) when R1 tied to
GND
VOUT = ((R2+R1)/R1) x (VIN-VINB) when R1 tied to VREF
Choice of Feedback Resistor
For a gain of one, VOUT may be shorted back to VFB, but
100
Ω-200Ω improves the bandwidth. For gains greater than
one, there is little to be gained from choosing resistor R1
value below 200
Ω, for it would only result in increased power
dissipation and potential signal distortion. Above 200
Ω, the
bandwidth response will develop some peaking (for a gain of
one), but substantially higher R1 values may be used for
higher voltage gains, such as up to 1k
Ω at a gain of four
before peaking will develop.
Capacitance Considerations
As with many high bandwidth amplifiers, the EL2142 prefers
not to drive highly capacitive loads. It is best if the
capacitance on VOUT is kept below 10pF if the user does not
want gain peaking to develop. The VFB node forms a
potential pole in the feedback loop, so capacitance should
be minimized on this node for maximum bandwidth.
The amount of capacitance tolerated on any of these nodes
in an actual application will also be dependent on the gain
setting and the resistor values in the feedback network.
Typical Applications Circuits
FIGURE 1. TYPICAL TWISTED PAIR APPLICATION
50
Ω
VFB
50
Ω
EL2142
VIN
VINB
VREF
VOUT
100
Ω
FIGURE 2. COAXIAL CABLE DRIVER PAIR APPLICATION
EL2142
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