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參數(shù)資料
| 型號(hào)： | EK4355 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192KHZ 24BIT 6CH DAC FOR DVD AUDIO |
| 中文描述： | 192kHz的24位6路援會(huì)的DVD音頻 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 160K |
| 代理商： | EK4355 |
ASAHI KASEI
[AK4355]
MS0063-E-01
2002/07
- 15 -
n
System Reset
The AK4355 should be reset once by bringing PDN= ”L” upon power-up. The AK4355 is powered up and the internal timing
starts clocking by LRCK “
↑
” after exiting reset and power down state by MCLK. The AK4355 is in the power-down mode
until MCLK and LRCK are input.
n
Power-down
The AK4355 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
Each DAC can be powered down by each power-down bit (PW1-3) “0”. In this case, the internal register values are not
initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if
the click noise influences system application.
Normal Operation
Internal
State
PDN
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1)
(3)
(6)
DZFL/DZFR
External
MUTE
(5)
(3)
(1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The ext ernal clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
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