參數(shù)資料
型號(hào)： EFM32TG230F32
廠商： Energy Micro
文件頁數(shù)： 18/136頁
文件大?。?/td> 0K
描述： MCU 32BIT 32KB FLASH 64-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 914-1035-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
114
www.energymicro.com
The Cortex-M3 MPU memory map is unified. This means instruction accesses and data accesses have
same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a
memory management fault. This causes a fault exception, and might cause termination of the process
in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically
based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types, see Section 2.2.1 (p. 15) .
Table 4.37 (p. 114) shows the possible MPU region attributes. Please not that the Shareability
and cache behavior attributes are usually not relevant for the EFM32 devices since these are not
used by other bus masters. However, these can be useful together with the DMA Controller. See
Section 4.5.9.1 (p. 123) for guidelines on using these attributes.
Table 4.37. Memory attributes summary
Memory
type
Shareability
Other attributes
Description
Strongly-
ordered
-
All accesses to Strongly-ordered memory occur in program
order. All Strongly-ordered regions are assumed to be shared.
Device
Shared
-
Memory-mapped peripherals that several processors share.
Non-shared
-
Memory-mapped peripherals that only a single processor uses.
Normal
Shared
Non-cacheable Write-
through Cacheable Write-
back Cacheable
Normal memory that is shared between several processors.
Non-shared
Non-cacheable Write-
through Cacheable Write-
back Cacheable
Normal memory that only a single processor uses.
Use the MPU registers to define the MPU regions and their attributes. The MPU registers are:
Table 4.38. MPU registers summary
Address
Name
Type
Required
privilege
Reset value
Description
0xE000ED90
TYPE
RO
Privileged
0x00000800
0xE000ED94
CTRL
RW
Privileged
0x00000000
0xE000ED98
RNR
RW
Privileged
0x00000000
0xE000ED9C
RBAR
RW
Privileged
0x00000000
0xE000EDA0
RASR
RW
Privileged
0x00000000
0xE000EDA4
RBAR_A1
RW
Privileged
0x00000000
Alias of RBAR, see Section 4.5.4 (p. 117)
0xE000EDA8
RASR_A1
RW
Privileged
0x00000000
Alias of RASR, see Section 4.5.5 (p. 117)
0xE000EDAC
RBAR_A2
RW
Privileged
0x00000000
Alias of RBAR, see Section 4.5.4 (p. 117)
0xE000EDB0
RASR_A2
RW
Privileged
0x00000000
Alias of RASR, see Section 4.5.5 (p. 117)
0xE000EDB4
RBAR_A3
RW
Privileged
0x00000000
Alias of RBAR, see Section 4.5.4 (p. 117)
0xE000EDB8
RASR_A3
RW
Privileged
0x00000000
Alias of RASR, see Section 4.5.5 (p. 117)
4.5.1 MPU Type Register
The TYPE register indicates how many regions the MPU supports. See the register summary in
Table 4.38 (p. 114) for its attributes. The bit assignments are:
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