參數(shù)資料
型號(hào): EDS2532AABJ-6B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M bits SDRAM (8M words ?32 bits)
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90
封裝: ROHS COMPLIANT, FBGA-90
文件頁數(shù): 32/48頁
文件大?。?/td> 614K
代理商: EDS2532AABJ-6B-E
EDS2532AABJ-6B
Data Sheet E0509E30 (Ver. 3.0)
32
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
DQ
READA
READ
out A0
out A1
out B0
out B1
CL= 3
BL = 4
bank0
Read A
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
CLK
Command
BS
DQ
WRITA
WRIT
in B1
in B2
in B3
in A0
in A1
in B0
BL= 4
bank0
Write A
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
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