參數(shù)資料
型號: EDS2532AABH-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: GT 3C 3#0 PIN PLUG
中文描述: 8M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90
封裝: LEAD FREE, FBGA-90
文件頁數(shù): 5/48頁
文件大?。?/td> 578K
代理商: EDS2532AABH-75-E
EDS2532CABH
Data Sheet E0395E40 (Ver. 4.0)
5
DC Characteristics 1 (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
IDD1
125
mA
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
1, 2, 3
Standby current in power down
IDD2P
3
mA
6
Standby current in power down
(input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Active standby current in non
IDD2PS
2
mA
CKE = VIL, tCK =
7
IDD2N
20
mA
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
4
IDD2NS
9
mA
8
IDD3P
4
mA
1, 2, 6
IDD3PS
3
mA
CKE = VIL, tCK =
2, 7
IDD3N
50
mA
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
,
/CS = VIH
tCK = tCK (min.),
BL = 4
1, 2, 4
30
mA
2, 8
Burst operating current
IDD4
-75
-1A
-75
-1A
125
265
255
mA
1, 2, 5
Refresh current
IDD5
mA
tRC = tRC (min.)
3
Self refresh current
IDD6
3
mA
VIH
VDD – 0.2V
VIL
0.2V
VIH
VDD – 0.2V
VIL
0.2V
Self refresh current
(L-version)
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
IDD6
-XXL
1
mA
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