參數(shù)資料
型號: EDS1232CATA
廠商: Elpida Memory, Inc.
英文描述: 128M bits SDRAM
中文描述: 128兆位內(nèi)存
文件頁數(shù): 41/55頁
文件大?。?/td> 564K
代理商: EDS1232CATA
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
41
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
Bank 0
Active
ACT
ROW
ACT
ROW
Bank 0
Active
tRC
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
Bank 0
Active
Bank 3
Active
ACT
ROW:0
ACT
ROW:1
tRRD
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Command
Address
Mode
Register Set
Bank
Active
MRS
IMRD
ACT
BS & ROW
OPCODE
Mode register set to Bank active command interval
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