參數(shù)資料
型號(hào)： EDS1232CATA-75
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M bits SDRAM
中文描述： 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝： PLASTIC, TSOP2-86
文件頁(yè)數(shù)： 29/55頁(yè)
文件大?。?/td> 564K
代理商： EDS1232CATA-75
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
29
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
WRIT
CLK
Command
DQ
ACT
Row
Column
in 0
in 6
in 7
Address
in 1
in 4
in 5
in 3
BL = 1
BL = 2
BL = 4
BL = 8
tRCD
in 0
in 0
in 0
in 1
in 1
in 2
in 2
in 3
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CLK
Command
DQ
ACT
Row
Column
in 0
Address
tRCD
Single write
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