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參數(shù)資料
| 型號： | EDI88512CAF32B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 熱敏電阻 |
| 英文描述： | NTC Thermistor; Series:PANR; Thermistor Type:NTC; Resistance:1kohm; Beta:3500; Package/Case:Radial; Leaded Process Compatible:Yes; Mounting Type:Through Hole; R/T Curve:M; Terminal Type:Radial Leaded RoHS Compliant: Yes |
| 中文描述： | 512Kx8單片的SRAM，貼片5962-95600 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 268K |
| 代理商： | EDI88512CAF32B |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
■
Access Times of 15, 17, 20, 25, 35, 45, 55ns
■
Data Retention Function (LPA version)
■
TTL Compatible Inputs and Outputs
■
Fully Static, No Clocks
■
Organized as 512Kx8
■
Commercial, Industrial and Military Temperature Ranges
■
32 lead JEDEC Approved Evolutionary Pinout
Ceramic Sidebrazed 600 mil DIP (Package 9)
Ceramic Sidebrazed 400 mil DIP (Package 326)
Ceramic 32 pin Flatpack (Package 344)
Ceramic Thin Flatpack (Package 321)
Ceramic SOJ (Package 140)
■
36 lead JEDEC Approved Revolutionary Pinout
Ceramic Flatpack (Package 316)
Ceramic SOJ (Package 327)
Ceramic LCC (Package 502)
■
Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolu-
tionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-
come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The cen-
ter pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
A Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
36 P
IN
T
OP
V
IEW
P
IN
D
ESCRIPTION
I/O
0-7
Data Inputs/Outputs
A
0-18
Address Inputs
WE
Write Enables
CS
Chip Selects
OE
Output Enable
V
CC
Power (+5V ±10%)
V
SS
Ground
NC
Not Connected
B
LOCK
D
IAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A
-18
I/O
-7
WE
CS
OE
FIG. 1
PIN CONFIGURATION
32 P
IN
T
OP
V
IEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
Aug. 2002 Rev. 9
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| EDI88512CAF32M | 512Kx8 Monolithic SRAM, SMD 5962-95600 |
| EDI88512CAF36B | 512Kx8 Monolithic SRAM, SMD 5962-95600 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EDI88512CAF32C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 Monolithic SRAM, SMD 5962-95600 |
| EDI88512CAF32I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 Monolithic SRAM, SMD 5962-95600 |
| EDI88512CAF32M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 Monolithic SRAM, SMD 5962-95600 |
| EDI88512CAF36B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 Monolithic SRAM, SMD 5962-95600 |
| EDI88512CAF36C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 Monolithic SRAM, SMD 5962-95600 |
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