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參數(shù)資料
| 型號： | EDI88130LPS17TC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 17 ns, CDIP32 |
| 封裝： | 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 499K |
| 代理商： | EDI88130LPS17TC |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI88130CS
March 2002
Rev. 11
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
ADDRESS
DATA I/O
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
READ CYCLE 2 (CS1# AND/OR CS2 CONTROLLED, WE# HIGH)
ADDRESS
DATA I/O
t
AVQV
t
E1LQV
t
GLQV
t
GLQX
t
E1LQX
t
E1LICCH
t
AVAV
t
E1HQZ
t
E1HICCL
t
GHQZ
OE#
Icc
CS1#
CS2
t
E2HICCH
t
E2HQX
t
E2LICCL
t
E2HQV
FIGURE 2 – TIMING WAVEFORM - READ CYCLES
FIGURE 4 – WRITE CYCLES 2
FIGURE 3 – WRITE CYCLE 1
ADDRESS
DATA IN
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
t
AVWH
t
WLWH
t
WHAX
t
E2HWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
t
E1LWH
CS1#
DATA OUT
WE#
CS2
ADDRESS
DATA I/O
WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED
t
E1LE1H
t
E1HAX
t
DVE1H
t
E1HDX
t
AVAV
CS1#
WE#
CS2
t
AVE1L
ADDRESS
DATA I/O
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
t
E2HE2L
t
E2LAX
t
DVE2L
t
E2LDX
t
AVAV
CS1#
WE#
CS2
t
AVE2H
WRITE CYCLES 3
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PDF描述 |
|---|---|
| EDI88130LPS17CM | 128K X 8 STANDARD SRAM, 17 ns, CDIP32 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI88130LPS20CB | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, LOW POWER, 2 - Bulk |
| EDI88130LPS20CI | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, LOW POWER, 2 - Bulk |
| EDI88130LPS20FB | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, LOW POWER, 2 - Bulk |
| EDI88130LPS20LB | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, LOW POWER, 2 - Bulk |
| EDI88130LPS20LI | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, LOW POWER, 2 - Bulk |
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