參數(shù)資料
型號: EDI88128LP85CB
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 85 ns, CDIP32
封裝: 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
文件頁數(shù): 5/8頁
文件大小: 386K
代理商: EDI88128LP85CB
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI88128C
April 2005
Rev. 17
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
ADDRESS
DATA IN
WRITE CYCLE 2 - EARLY WRITE, CS
1#
CONTROLLED
t
WLEH
t
EHAX
t
ELEH
t
DVEH
t
EHDX
t
AVAV
DATA VALID
WE#
CS
1#
t
AVEL
CS
2
ADDRESS
DATA IN
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
t
WLSL
t
SLAX
t
SHSL
t
DVSL
t
SLDX
t
AVAV
DATA VALID
WE#
CS1#
t
AVSH
CS2
FIGURE 2 – TIMING WAVEFORM — READ CYCLE
FIGURE 4 – WRITE CYCLE 2
FIGURE 3 – WRITE CYCLE 1
WRITE CYCLE 3
ADDRESS
DATA I/O
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA I/O
READ CYCLE 2 (WE# HIGH)
t
AVQV
t
ELQV
t
GLQV
t
GLQX
t
ELQX
t
SHQV
t
SHQX
t
AVAV
t
EHQZ
t
GHQZ
OE#
CS2
t
SLQZ
CS1#
ADDRESS
DATA IN
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
WHDX
t
AVWL
t
AVAV
DATA VALID
HIGH Z
WE#
t
SHWH
CS1#
DATA OUT
CS
2
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