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參數(shù)資料
| 型號： | EDI2DL32256V35BC |
| 英文描述： | 256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,3.5ns,256Kx32同步流水線脈沖靜態(tài)RAM) |
| 中文描述： | 256Kx32同步管材突發(fā)SRAM的3.3（3.3伏，3.5ns，256Kx32同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 96K |
| 代理商： | EDI2DL32256V35BC |
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
Various
A0-17
Input
Addresses: These inputs are registered and must meet setup and hold times around the rising edge
Synchronous
of CLK.
L5,G5
BE0\,BE1\,
Input
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ BE2\, BE3\ cycle. BE0\ controls
G3,L3
BE2\,BE3\
Synchronous
DQ0-7. BE1\ controls DQ8-15. BE2\ controls DQ16-23. BE3\ controls DQ24-31
M4
BWE\
Input
Byte Write Enable: This active LOW input gates byte write operations and must meet the setup and hold
Synchronous
times around the rising edge of CLK.
K4
CLK
Input
Clock:This signal registers the addresses, data, chip enables, write control and burst control inputs on
Synchronous
its rising edge. All synchronous inputs must meet setup and hold times around the clockís rising edge.
E4
CE\
Input
Chip Enable: This active LOW inputs is used to enable the device.
Synchronous
F4
OE\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers
B4
ADSC\
Input
Address Status Controller: This active LOW input causes device to be deselected or selected along with new
Synchronous
external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
R3
MODE
Input
Static Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or
HIGH on this pin selects INTERLEAVED BURST.
T7
ZZ
Input
Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal
Synchronous
operation, this input has to be either LOW or NC (no connect)
Various
DQ0-31
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31
Various
Vcc
Supply
Core power supply: +3.3V -5%/+5%
Various
Vss
Ground
Operation
Address Used
CE\
ADSC\
WRITE\
OE\
DQ
Deselected Cycle, Power Down
None
H
L
X
High-Z
WRITE Cycle, Begin Burst
External
L
X
D
READ Cycle, Begin Burst
External
L
H
L
Q
READ Cycle, Begin Burst
External
L
H
High-Z
READ Cycle, Suspend Burst
Current
X
H
L
Q
READ Cycle, Suspend Burst
Current
X
H
High-Z
READ Cycle, Suspend Burst
Current
H
L
Q
READ Cycle, Suspend Burst
Current
H
High-Z
WRITE Cycle, Suspend Burst
Current
X
H
L
X
D
WRITE Cycle, Suspend Burst
Current
H
L
X
D
NOTE:
1. X means ìdonít care, H means logic HIGH. L means logic LOW.
2a.WRITE\ = L, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals LOW
2b.WRITE\ = H, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals HIGH
3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle
5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH though
out the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
TRUTH TABLE
相關(guān)PDF資料 |
PDF描述 |
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| EDI2DL32256V38BC | 256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,3.8ns,256Kx32同步流水線脈沖靜態(tài)RAM) |
| EDI2DL32256V40BC | 256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,4.0ns,256Kx32同步流水線脈沖靜態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2DL32256V38BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| EDI2DL32256V40BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| EDI2DL32256V40BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| EDI2DL32256V-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SSRAM MCP |
| EDI2DL32256V-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TMS320C6202. TMS320C6203. TMS320C6204. TMS320C6 Families |
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