- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384277 > EDD2516AETA-5B-E (ELPIDA MEMORY INC) 256M bits DDR SDRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | EDD2516AETA-5B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M bits DDR SDRAM |
| 中文描述： | 16M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 492K |
| 代理商： | EDD2516AETA-5B-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
EDD2508AETA, EDD2516AETA
Data Sheet E0859E50 (Ver. 5.0)
22
Auto-refresh command [REF]
This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The average refresh cycle is 7.8
μ
s. The output buffer becomes High-Z after auto-
refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can
be issued tRFC
after the last auto-refresh command.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the self-
refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode
continues while CKE is held low. No internal refresh operation occurs during the power down mode. [PDEN] do not
disable DLL.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.
To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After
the exit, input auto-refresh command within 7.8
μ
s.
Power down exit [PDEX]
The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD2516AETA-5C-E | 256M bits DDR SDRAM |
| EDD2516AETA-6B-E | 256M bits DDR SDRAM |
| EDD2516AETA-7B-E | 256M bits DDR SDRAM |
| EDD2516AKTA-5-E | 256M bits DDR SDRAM (16M words x16 bits, DDR400) |
| EDD2516AKTA-5C-E | 256M bits DDR SDRAM (16M words x16 bits, DDR400) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD2516AETA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2516AETA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2516AETA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2516AETA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2516AKTA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。