參數(shù)資料
型號： EDD1216AATA-5B-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
中文描述： 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁數(shù)： 7/49頁
文件大?。?/td> 569K
代理商： EDD1216AATA-5B-E
EDD1216AATA
Data Sheet E0444E40 (Ver. 4.0)
7
-6B
-7A
-7B
Parameter
Address and control input setup
time
Symbol
min.
max.
min.
max.
min.
max.
Unit
Notes
tIS
0.75
—
0.9
—
0.9
—
ns
8
Address and control input hold time tIH
0.75
—
0.9
—
0.9
—
ns
8
Address and control input pulse
width
Mode register set command cycle
time
Active to Precharge command
period
Active to Active/Auto refresh
command period
Auto refresh to Active/Auto refresh
command period
tIPW
2.2
—
2.2
—
2.2
—
ns
7
tMRD
2
—
2
—
2
—
tCK
tRAS
42
120000
45
120000
45
120000
ns
tRC
60
—
67.5
—
67.5
—
ns
tRFC
72
—
75
—
75
—
ns
Active to Read/Write delay
tRCD
18
—
20
—
20
—
ns
Precharge to active command
period
tRP
18
—
20
—
20
—
ns
Active to Autoprecharge delay
tRAP
tRCD min. —
tRCD min. —
tRCD min. —
ns
Active to active command period
tRRD
12
—
15
—
15
—
ns
Write recovery time
tWR
15
—
15
—
15
—
ns
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
tDAL
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
tCK
13
tWTR
1
—
1
—
1
—
tCK
Average periodic refresh interval
tREF
—
15.6
—
15.6
—
15.6
μs
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
相關(guān)PDF資料
PDF描述
EDD1216AATA-5C-E 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
EDD1216AATA-7A-E 128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA-7B-E 128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AJTA 128M bits DDR SDRAM
EDD1216AJTA-5B-E 128M bits DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD1216AATA-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400)
EDD1216AATA-6B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA-7A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA-7B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AJBG 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
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