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參數資料
| 型號： | EBS26UC6APS-80L |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | AC Solid State Switch using optical coupling with dual power SCR outputs |
| 中文描述： | 32M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, DMA144 |
| 封裝： | SODIMM-144 |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 145K |
| 代理商： | EBS26UC6APS-80L |
Document No. E0225E20 (Ver. 2.0)
Date Published December 2001 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001
C
DATA SHEET
256MB SDRAM S.O.DIMM
EBS26UC6APS (32M words
×
64 bits, 2 bank)
Description
The EBS26UC6APS is 32M words
×
64 bits, 2 banks
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 8 pieces of
256M bits SDRAM (EDS2516APTA) sealed in TSOP
package. This module provides high density and large
quantities of memory in a small space without utilizing
the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.
Features
Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
144-pin socket type small outline dual in line memory
module (S.O.DIMM)
PCB height: 31.75mm (1.25inch )
Lead pitch: 0.80mm
3.3V power supply
Clock frequency: 100MHz/133MHz (max.)
LVTTL interface
Data bus width:
×
64 non-ECC
Single pulsed /RAS
4 Banks can operates simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, Full page
2 variations of burst sequence
Sequential
Interleave
Programmable /CAS latency (CL): 2, 3
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
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