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參數(shù)資料
| 型號： | EBD52UC8AKFA-5 |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | JT 12C 8#20 4#16 SKT PLUG |
| 中文描述： | 512MB的DDR SDRAM的內(nèi)存緩沖（6400字× 64位，2個等級） |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 199K |
| 代理商： | EBD52UC8AKFA-5 |
Document No. E0367E20 (Ver. 2.0)
Date Published March 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2003
PRELIMINARY DATA SHEET
512MB DDR SDRAM SO DIMM
EBD52UC8AKDA
(64M words
×
64 bits, 2 Ranks)
Description
The EBD52UC8AKDA is 64M words
×
64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 16 pieces of 256M
bits DDR SDRAM sealed in TCP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TCP on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
200-pin socket type small outline dual in line memory
module (SO DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs and DM are synchronized with
DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBD52UC8AKFA-5B | 512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5C | JT 55C 55#22D SKT PLUG |
| EBD52UC8AKDA | 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKDA-7A | 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKDA-7B | 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD52UC8AKFA-5B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5C | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
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