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參數(shù)資料
| 型號(hào)： | EB2060X |
| 英文描述： | Evaluation board |
| 中文描述： | 評(píng)估板 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 873K |
| 代理商： | EB2060X |
_______________
__ EB-2060x
2
Details are subject to change without notice.
DESIGN OVERVIEW
The
EB-2060x
is
an
all-digital
amplifier
evaluation board that demonstrates Apogee’s
DDX-2000/2060 chip set solution.
The board
features – coaxial and optical S/PDIF digital
interfaces,
volume
and
balance
controls,
expansion headers for off-board processing, and
local power regulation enabling single supply
operation from +10 to +28 VDC. The all-digital
amplifier board may be configured as either 2 x
35W into 8
or 1 x 70W into 4.
DDX-2000/2060 OVERVIEW
The DDX-2000 Controller is a 3.3V digital
integrated circuit that converts serial PCM digital
audio signals into Apogee's patented damped
ternary outputs.
The device supports two
modes of digital volume control, muting and anti-
clipping functions.
A block diagram of the
device is shown in Figure 1.
Figure 1 - DDX-2000 Functional Diagram
The DDX-2060 Power Device is a dual channel
H-Bridge that can deliver over 35 watts per
channel of audio output power. The DDX-2060
includes;
a logic interface, integrated bridge
drivers, high efficiency MOSFET outputs and
protection circuitry. Two logic level signals per
channel
are
used
to
control
high-speed
MOSFET switches to connect the speaker load
to the input supply or to ground in a bridge
configuration, according to Apogee's patented
damped ternary PWM. The DDX-2060 includes
over-current,
thermal,
and
over-voltage
protection
and
under-voltage
lockout
with
automatic recovery. A thermal warning status is
also provided.
Figure 2 - DDX-2060 Block Diagram
SCHEMATIC DESCRIPTION
S/PDIF INPUT INTERFACE (FIG. 3A)
The EB-2060x accommodates either a coaxial
or an optical S/PDIF digital audio interface.
Either input may be selected by moving jumper
J2. Connect J2 pins 1-2 for coaxial or J2 pins 2-
3 for optical S/PDIF. A Crystal CS8415A digital
audio interface receiver is utilized to convert the
incoming S/PDIF signal to serial I
2S used by the
DDX-2000. The receiver also recovers a 256*Fs
clock synchronized to the incoming signal which
is used as the master clock to the DDX-2000.
The design will support sample rates from below
32 kHz to above 48 kHz. The receiver PLL out-
of-lock signal is used to mute the amplifier’s
output when a valid S/PDIF signal is not present.
Zero ohm jumpers R6,R9,R10,R11,R42 are
provided to disconnect the outputs of the S/PDIF
receiver from the inputs to the DDX-2000 so that
external
signals
may
be
applied
via
the
expansion header J7, (see Fig. 3D).
DIGITAL SIGNAL PROCESSING (FIG. 3B)
The DDX-2000 converts serial I
2S digital audio
signals
into
pulse-width-modulated
digital
signals output at 8*Fs, according to Apogee’s
patented damped ternary architecture. Signals
from the S/PDIF receiver are applied as inputs
to the DDX processor and signals from the DDX
processor are applied to the inputs of the DDX
power stage.
A low-cost microcontroller with an ADC is used
to implement the volume and balance controls.
The amplifier’s volume and balance levels are
SERIAL
INTERFACE
VOLUME/
GAIN
PWM
GENERATION
ANTI-
CLIPPING
SYSTEM
CLOCKING
SCLK
SDATA
LRCLK
VMODE
VCLK/UP
VDATA/DN
ACE
OUTL[1:2]
OUTR[1:2]
XI XO LPIN LPOUT
MUTE
Logic I/F
and Decode
Left
H-Bridge
Protection
Circuitry
INL[1:2]
INR[1:2]
PWRDN
OUTPL
FAULT
VL
TRI-STATE
OUTNL
OUTPR
OUTNR
TWARN
Regulators
Right
H-Bridge
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