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參數(shù)資料
| 型號： | EA-C10 |
| 廠商： | NEC Corp. |
| 英文描述： | CMOS Embedded Array (ASIC)(CMOS 嵌入式陣列) |
| 中文描述： | 嵌入式陣列（專用集成電路）的CMOS（嵌入式陣列的CMOS） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 54K |
| 代理商： | EA-C10 |
NEC Electronics Inc.
EA-C10
2.5-Volt, 0.25-Micron (drawn)
CMOS Embedded Array
March 1997
Preliminary
A12503EU1V0DS00
EA-C10 Series Features
EA-C10 Series Benefits
0.25 μm drawn (0.18 μm L-effective) CMOS process
Ultra-high density cell structure with high performance
Advanced embedded array architecture
Fast TAT and high integration of embedded megafunctions
Available gate counts from 206K to 7 million gates
Support for a wide range of high-complexity systems
Optimized 2.5V architecture (operates down to 1.8V)
Highest speed at ultra-low power consumption
Significant low power dissipation of 0.14 μW/MHz/gate
New application possibilities and new system solutions
Ultra-high pin count using 40 μm pad pitch
Increased I/O density to achieve smaller die sizes
Special power rail structure, multi-oxide process
Mixed 2.5V / true 3.3V I/O for full system compatibility
Cell-based I/O structure including LVDS, HSTL, GTL+, PCI
Flexible adaptation to system requirements
Embedding of analog macros including DACs, ADCs
Mixed-signal design options
Advanced packages such as TapeBGA, Flip Chip+BGA
Cost-effective and state-of-the-art packaging
NEC’s OpenCAD
design environment
Flexible design flow for short design times
Applications
The EA-C10 family is ideal for applications where high
density is mandatory and a short time-to-market path is
required. For example, RAM-dominated designs can be
realized with reduced die size and a reasonable turnaround
time. EA-C10 is well-suited for designs that may require
rework, because the logic function portion of the design
uses gate array primitives created just by the final metal
masks. Typical applications include engineering
workstations, telecommunications systems, advanced
graphics and low power applications where very high
performance is required.
Figure 1. Embedded Array Core Integration
Table 1. EA-C10 Series Features and Benefits
Description
The high-speed 0.25 μm drawn (0.18 μm L-effective)
EA-C10 embedded array family offers both support for
embedded high-density macros as well as the short
turnaround time of a gate array resulting in a time-to-
market advantage. In this product, NEC combines high-
performance CMOS gate array primitives with diffused,
embedded megafunctions such as RAM, ROM, CPU,
DSP and analog cores.
EA-C10 also uses a cell-based I/O structure that allows a
flexible adaptation to the system requirements. State-of-
the-art interface macros for high-speed or special signaling
systems are also supported, such as PCI, HSTL, GTL+,
LVDS, p-ECL, and IEEE1394. Analog functions like DACs,
ADCs and PLLs also can be incorporated within the I/O
area.
Process
EA-C10 ASICs are manufactured with NEC’s advanced
titanium-silicide (Ti-Si) process. The chip layout may use
between three and five metal layers (Al). As the EA-C10
ASIC family follows basically a gate array approach, it
offers short turnaround times for silicon processing and
lower development costs compared to cell-based ASICs.
The turnaround time is kept short by fixing the embedded
core locations and beginning prototype fabrication in
parallel with place and route design steps.
High Density
Memory
Analog
Macro
Logic
Function
Cell-Based
I/O Cells
High Density
Cell-Based
Compiled Memory
Gate Array
Primitives
(Sea-of-Gate)
Advanced Core
and
Analog Functions
Gate Array
Base Master
Core
or
Megafunction
OpenCAD is a registered trademark of NEC Electronics Inc.
All non-NEC trademarks are the property of their respective owners.
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