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參數(shù)資料
| 型號： | E629-EDGE629 |
| 英文描述： | 1 GHz Timing Deskew and Quad Fanout Element |
| 中文描述： | 1 GHz的定時偏移校正和四扇出元素 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 137K |
| 代理商： | E629-EDGE629 |
10
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge629
TARGET
Circuit Description
(continued)
Timing Inputs
IN/IN* and IN0/IN0* – IN3/IN3* are high speed
differential inputs which require >300 mV of differential
input voltage for reliable switching.
These inputs may receive differential input signals with
amplitudes up to 3.3V. This wide range input voltage
compliance allows CMOS signals to drive the Edge629
directly.
The inputs may go all the way up to VCC and still not
cause any saturation. The Edge629 will operate at full
performance under these input conditions.
Do not leave any differential inputs floating as they will
be in an indeterminate state. All unused inputs must be
tied to either a high or low level. Connecting unused
timing inputs to VCC is an acceptable method to make
an input high. However, to make an input low, it must
be connected to VEE +2.0V or higher.
Input Mux Select
Each delay channel can select its input from one of two
sources. If Mux Select is high (SEL > SEL*), IN/IN* will
be selected for all four channels. If Mux Select is low
(SEL < SEL*), IN0/IN0* – IN3/IN3* will be selected for
each channel.
SEL/SEL* have internal pull-up/pull-down resistors which,
when left floating, place the chip in fanout mode.
Data Interface Digital Inputs
All data digital inputs are standard, single ended ECL
inputs with Vbb = –1.3V relative to VCC. However, all
digital inputs may receive input signals anywhere between
VCC and VEE. This wide input voltage compliance allows
CMOS signals to program the Edge629 without causing
saturation problems.
All digital interface inputs are "3.3V rail to rail" CMOS
compatible provided VCC = +3.3V and VEE = –2V.
CK, SDI, and UPDATE all have an internal pull-down
resistor network to establish a default condition of a
logical 0 when left floating. CS has a large (~50 K
)
internal pull-up resistor to VCC to establish a default
condition of a logical 1 when left floating.
For optimal performance, all data interface digital inputs
should be static when the Edge 629 is actively delaying
signals. (However, it is acceptable if CK continues to
run.)
Timing Outputs
OUT0/OUT0* – OUT3/OUT3* are standard differential
ECL open emitter outputs.
Compensation Pins
COMP0, COMP1, COMP2, and COMP3 are op amp
compensation pins requiring external 100 pF capacitors
to VEE.
SEL*
VCC
SEL
50K
50K
VEE
VCC
*
L
E
S
/
L
E
Se
c
r
u
o
S
t
u
p
n
I
0*
3
N
I
/
3
N
I
–
*
0
N
I
/
0
N
I
1*
N
I
/
N
I
CK, SDI, UPDATE
VCC
CS
VEE
VCC
50K
50K
50K
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