
 1057
SAM4CP [DATASHEET]
43051E–ATPL–08/14
E
Reset Controller (RSTC)
Changed “VDD_REG_BU” by “VDDBU”.
Removed section “Brownout Manager”.
Section 15.4.3.2 “Backup Reset” on page 270
 replaced “core_backup_reset” with
“vddcore_nreset”.
Section 15.5.1 “Reset Controller Control Register” on page 274
 modified EXTRST
description.
Section 15.5.2 “Reset Controller Status Register” on page 275
 modified bit descriptions.
Section 15.5.3 “Reset Controller Mode Register” on page 276
 modified ERSTL bit
description.
Real-time Timer (RTT)
Modified 
Section 16.4 “Functional Description” on page 279
.
Section 16.5.1 “Real-time Timer Mode Register” on page 281
 modified RTPRES description.
Section 16.5.2 “Real-time Timer Alarm Register” on page 282
 modified ALMV description.
Real-time Clock (RTC)
Section 17.5.7 “RTC Accurate Clock Calibration” on page 289
 modified paragraph on
calibration circuitry.
Section 17.6.2 “RTC Mode Register” on page 293
 modified descriptions of NEGPPM,
HIGHPPM and THIGH bits.
Added 
Section 17.6.17 “RTC Write Protection Mode Register” on page 310
”
.
Reinforced Safety Watchdog Timer (RSWDT)
Added Windowed Watchdog in 
Section 19.2 “Embedded Characteristics” on page 318
and
Section 19.4 “Functional Description” on page 319
.
Updated 
Section 19.4 “Functional Description” on page 319
.
Modified 
Figure 19-2
.
Section 19.5.2 “Reinforced Safety Watchdog Timer Mode Register” on page 322
 added
notes.
Clock Generator
Figure 29-1
 and 
Figure 29-4
 updated for clarity.
Added 
Section 29.5.5 “Switching Main Clock between the Main RC Oscillator and Fast
Crystal Oscillator” on page 532
.
Power Management Controller (PMC)
Figure 30-1
 Updated for clarity.
Section 30.10 “Main Processor Fast Startup” on page 538
 updated for clarity.
Added 
Section 30.11 “Main Processor Startup from Embedded Flash” on page 539
.
Section 30.13 “Main Clock Failure Detector” on page 540
 updated for clarity.
Section 30.15 “Programming Sequence” on page 541
 updated for clarity.
Section 30.18.8 “PMC Clock Generator Main Clock Frequency Register” on page 556
updated MAINF bit description.
Chip Identifier (CHIPID)
Section 31.3.1 “Chip ID Register” on page 578
 (NVPSIZ: Nonvolatile Program Memory Size):
Changed information in row for Value 8.
Doc. Rev.
43051
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