
37
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Pseudo-code
1- // Enable Coprocessor Bus Master Clock in PMC System Clock Enable Register
(CPBMCK bit)
2- // Enables Coprocessor Clocks
PMC System Clock Enable Register (CPCK bit)
// Set Coprocessor Clock Prescaler and Source
In PMC MCKR: Coprocessor Programmable Clock Prescaler (CPPRES bit fields)
// Choose coprocessor main clock source
In PMC MCKR: Coprocessor Master Clock Selection (CPCSS bit fields)
3- // Release coprocessor peripheral reset
In Reset Controller Coprocessor Mode Register (CPEREN bit)
4- // Enable Core 1 SRAM1 and SRAM2 Memories
In PMC PCER: Peripheral ID 42 (SRAM)
5- // AT THIS POINT Core 1 application code must be loaded from Flash into SRAM1.
6- // Release coprocessor reset
In Reset Controller Coprocessor Mode Register (CPROCEN bit)
8.1.5.4 Sub-system 1 Start-up Time
Table 8-3
provides the start-up time of sub-system 1 in terms of the number of clock cycles for different CPU speeds. The
figures in this table take into account the time to copy 16 Kbytes of code from Flash into SRAM1 using the ‘memcopy’
function from the standard C library and to release Core 1 reset signal. The start-up time of the device from power-up is
not taken into account
.
Table 8-3.
Sub-system 1 start-up time
Core Clock (MHz)
Flash Wait State
Core Clock cycles
Time
21
0
44122
2.1 ms
42
1
45158
1.07 ms
63
2
46203
735
μ
s
85
3
47242
55
μ
s
106
4
48284
455
μ
s
120
5
49329
411
μ
s