參數(shù)資料
型號: DSPIC33FJ32GP202-E/MM
廠商: Microchip Technology
文件頁數(shù): 59/176頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 32K 28QFN
產(chǎn)品培訓模塊: Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 61
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 652 (CN2011-ZH PDF)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
149
AT89C5131
4136C–USB–04/05
Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET LOW
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T
CLK PERIPH, where TCLK PERIPH =
1/F
CLK PERIPH. To make the best use of the WDT, it should be serviced in those sections
of code that will periodically be executed within the time required to prevent a WDT
reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s at F
OSCA = 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 108.
Table 107. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
7654
3210
--------
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參數(shù)描述
dsPIC33FJ32GP202-I/MM 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B DSC 28LD 32KB Flash40 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
dsPIC33FJ32GP202-I/SO 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B DSC 28LD 32KB Flash40 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
dsPIC33FJ32GP202-I/SP 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B DSC 28LD 32KB Flash40 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
dsPIC33FJ32GP202-I/SS 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 bit DSC 40MIPS 32KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
DSPIC33FJ32GP202T-E/MM 制造商:Microchip Technology Inc 功能描述: