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參數(shù)資料
| 型號(hào)： | DSPIC33FJ256GP510-I/PF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 123/197頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 256K 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | dsPIC33F DMAC Introduction to dsPIC33F Architecture Part 1 Asynchronous Stimulus Introduction to dsPIC33F Architecture Part 2 |
| 特色產(chǎn)品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | dsPIC™ 33F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | CAN，I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設(shè)備： | AC'97，欠壓檢測/復(fù)位，DMA，I²S，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 85 |
| 程序存儲(chǔ)器容量： | 256KB（256K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 32x10b/12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 654 (CN2011-ZH PDF) |
| 配用： | 876-1001-ND - DSPIC33 BREAKOUT BOARD DM300024-ND - KIT DEMO DSPICDEM 1.1 DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 MA330012-ND - MODULE DSPIC33 100P TO 84QFP MA330011-ND - MODULE DSPIC33 100P TO 100QFP DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 AC164323-ND - MODULE SKT FOR 100TQFP |
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2009 Microchip Technology Inc.
DS70286C-page 29
dsPIC33FJXXXGPX06/X08/X10
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler
is
a
33-bit
value
which
is
sign-extended to 40 bits. Integer data is inherently
represented as a signed two’s complement value,
where the Most Significant bit (MSb) is defined as a
sign bit. Generally speaking, the range of an N-bit two’s
complement integer is -2N-1 to 2N-1 - 1. For a 16-bit
integer, the data range is -32768 (0x8000) to 32767
(0x7FFF) including 0. For a 32-bit integer, the data
range
is
-2,147,483,648
(0x8000 0000)
to
2,147,483,647 (0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 - 21-N). For a 16-bit fraction, the Q15 data range is
-1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
product which has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions which include integer 16-bit
signed, unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The
data
accumulator
consists
of
a
40-bit
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
via the barrel shifter prior to accumulation.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true, or complement
data into the other input. In the case of addition, the
Carry/Borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the Carry/Borrow input is active-low and
the other input is complemented. The adder/subtracter
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS
register:
Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above and the SAT<A:B> (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
OA:
AccA overflowed into guard bits
2.
OB:
AccB overflowed into guard bits
3.
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
4.
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
5.
OAB:
Logical OR of OA and OB
6.
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic
warning
trap
when
set
and
the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register (refer to Section 7.0
“Interrupt Controller”) are set. This allows the user to
take immediate action, for example, to correct system
gain.
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| dsPIC33FJ256GP510T-I/PT | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU DSP 100LD 40MIPS 256KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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