參數(shù)資料
型號: DSPIC33FJ16MC304-I/PT
廠商: Microchip Technology
文件頁數(shù): 21/76頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 16K 44TQFP
產(chǎn)品培訓模塊: Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 160
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 652 (CN2011-ZH PDF)
配用: DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 28
2007-2012 Microchip Technology Inc.
3.7.3.2
Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac-
tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
For input data greater than 0x007FFF, data writ-
ten to memory is forced to the maximum positive
1.15 value, 0x7FFF.
For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000.
The Most Significant bit of the source (bit 39) is used to
determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
3.7.4
BARREL SHIFTER
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP accu-
mulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is pre-
sented to the barrel shifter between bit positions 16 and
31 for right shifts, and between bit positions 0 and 16
for left shifts.
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