參數(shù)資料
型號: DSPIC33FJ16GP304-I/PT
廠商: Microchip Technology
文件頁數(shù): 60/176頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 16K 44TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 160
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 652 (CN2011-ZH PDF)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
150
AT89C5131
4136C–USB–04/05
Table 108. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset value = XXXX X000
WDT During Power-down
and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C5131 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C5131 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
7
6
5
4
3
2
1
0
-
S2
S1
S0
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2 S1 S0 Selected Time-out
0
16384x2^(214 - 1) machine cycles, 16.3 ms at FOSCA = 12 MHz
0
1
16384x2^(215 - 1) machine cycles, 32.7 ms at FOSCA = 12 MHz
0
1
0
16384x2^(216 - 1) machine cycles, 65.5 ms at FOSCA = 12 MHz
0
1
16384x2^(217 - 1) machine cycles, 131 ms at FOSCA = 12 MHz
1
0
16384x2^(218 - 1) machine cycles, 262 ms at FOSCA = 12 MHz
1
0
1
16384x2^(219 - 1) machine cycles, 542 ms at FOSCA = 12 MHz
1
0
16384x2^(220 - 1) machine cycles, 1.05 s at FOSCA = 12 MHz
1
16384x2^(221 - 1) machine cycles, 2.09 s at FOSCA = 12 MHz
16384x2^S machine cycles
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