參數(shù)資料
型號: DSPIC33FJ128GP310-I/PF
廠商: Microchip Technology
文件頁數(shù): 22/90頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 128K 100TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC33F DMAC
Introduction to dsPIC33F Architecture Part 1
Asynchronous Stimulus
Introduction to dsPIC33F Architecture Part 2
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 654 (CN2011-ZH PDF)
配用: DM300024-ND - KIT DEMO DSPICDEM 1.1
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA330012-ND - MODULE DSPIC33 100P TO 84QFP
MA330011-ND - MODULE DSPIC33 100P TO 100QFP
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
AC164323-ND - MODULE SKT FOR 100TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
2005 Microchip Technology Inc.
Preliminary
DS70155C-page 27
dsPIC33F
8.4
Quadrature Encoder Interface
(QEI) Module
Quadrature encoders (also referred to as incremental
encoders or optical encoders) are used in position and
speed
detection
of
rotating
motion
systems.
Quadrature encoders enable closed-loop control of
many motor control applications, such as Switched
Reluctance (SR) Motor and AC Induction Motor
(ACIM).
Typically, three outputs termed, Phase A, Phase B and
INDEX, provide information that can be decoded to
provide information on the movement of the motor
shaft, including distance and direction.
A quadrature decoder captures the phase signals and
index pulse and converts the information into a numeric
count of the position pulses. Generally, the count will
increment when the shaft is rotating one direction and
decrement when the shaft is rotating in the other
direction.
The QEI module (Figure 8-3) includes:
Three input pins for two phase signals and index
pulse
Programmable digital noise filters on inputs
Quadrature decoder providing counter pulses and
count direction
16-bit up/down position counter
Count direction status
x2 and x4 count resolution
Two modes of Position Counter Reset
General Purpose16-Bit Timer/Counter mode
Interrupts generated by QEI or counter events
FIGURE 8-3:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
16-Bit Up/Down Counter
Comparator/
Max Count Register
Quadrature
Programmable
Digital Filter
QEA
Programmable
Digital Filter
INDX
1
Up/Down
Existing Pin Logic
UPDN
3
Encoder
Programmable
Digital Filter
QEB
Interface Logic
QEIM<2:0>
Mode Select
3
(POSCNT)
(MAXCNT)
PCDOUT
QEIIF
Event
Flag
Reset
Equal
2
TCY
1
0
TQCS
TQCKPS<1:0>
2
1, 8, 64, 256
Prescaler
Q
D
CK
TQGATE
QEIM<2:0>
Synchronize
Det
1
0
Sleep Input
0
1
UPDN_SRC
QEICON<11>
Zero Detect
0
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