參數(shù)資料
型號： DSPIC30F5013T-30I/PTG
廠商： Microchip Technology
文件頁數(shù)： 40/66頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 66K 80TQFP
標準包裝： 1,200
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設備： AC'97，欠壓檢測/復位，I²S，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 68
程序存儲器容量： 66KB（22K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 16x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
配用： DM300024-ND - KIT DEMO DSPICDEM 1.1
XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
DM300004-2-ND - BOARD DEMO DSPICDEM.NET 2
DM300004-1-ND - BOARD DEMO DSPICDEM.NET 1
AC30F007-ND - MODULE SKT FOR DSPIC30F 80TQFP
其它名稱： DSPIC30F5013T30I
2010 Microchip Technology Inc.
DS70102K-page 45
dsPIC30F Flash Programming Specification
11.8
Writing Code Memory
The procedure for writing code memory is similar to the
procedure for clearing the Configuration registers,
except that 32 instruction words are programmed at a
time. To facilitate this operation, working registers
W0:W5 are used as temporary holding registers for the
data to be programmed.
Table 11-8 shows the ICSP programming details,
including the serial pattern with the ICSP command
code, which must be transmitted Least Significant bit
first using the PGC and PGD pins (see Figure 11-2). In
Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for single-panel
programming of code memory. In Step 3, the 24-bit
starting destination address for programming is loaded
into the TBLPAG register and W7 register. The upper
byte of the starting destination address is stored to
TBLPAG, while the lower 16 bits of the destination
address are stored to W7.
To minimize the programming time, the same packed
instruction format that the programming executive uses
is utilized (Figure 8-2). In Step 4, four packed
instruction words are stored to working registers
W0:W5 using the MOV instruction and the read pointer
W6 is initialized. The contents of W0:W5 holding the
packed instruction word data is shown in Figure 11-4.
In Step 5, eight TBLWT instructions are used to copy the
data from W0:W5 to the write latches of code memory.
Since code memory is programmed 32 instruction
words at a time, Steps 4 and 5 are repeated eight times
to load all the write latches (Step 6).
After the write latches are loaded, programming is
initiated by writing to the NVMKEY and NVMCON
registers in Steps 7 and 8. In Step 9, the internal PC is
reset to 0x100. This is a precautionary measure to
prevent the PC from incrementing into unimplemented
memory when large devices are being programmed.
Lastly, in Step 10, Steps 2-9 are repeated until all of
code memory is programmed.
FIGURE 11-5:
PACKED INSTRUCTION
WORDS IN W0:W5
15
8
7
0
W0
lsw0
W1
MSB1
MSB0
W2
lsw1
W3
lsw2
W4
MSB3
MSB2
W5
lsw3
TABLE 11-8:
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
Command
(Binary)
Data
(Hexadecimal)
Description
Step 1: Exit the Reset vector.
0000
040100
000000
GOTO 0x100
NOP
Step 2: Set the NVMCON to program 32 instruction words.
0000
24001A
883B0A
MOV
#0x4001, W10
MOV
W10, NVMCON
Step 3: Initialize the write pointer (W7) for TBLWT instruction.
0000
200xx0
880190
2xxxx7
MOV
#<DestinationAddress23:16>, W0
MOV
W0, TBLPAG
MOV
#<DestinationAddress15:0>, W7
Step 4: Initialize the read pointer (W6) and load W0:W5 with the next 4 instruction words to program.
0000
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
MOV
#<LSW0>, W0
MOV
#<MSB1:MSB0>, W1
MOV
#<LSW1>, W2
MOV
#<LSW2>, W3
MOV
#<MSB3:MSB2>, W4
MOV
#<LSW3>, W5
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