參數(shù)資料
型號: DSPIC30F5011-20I/PT
廠商: Microchip Technology
文件頁數(shù): 145/220頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
標(biāo)準(zhǔn)包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測/復(fù)位,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲器容量: 66KB(22K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
其它名稱: DSPIC30F5011-20I/PTG
DSPIC30F501120/PT-ND
DSPIC30F501120IPT
DSPIC30F501120IPT-ND
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dsPIC30F5011/5013
DS70116J-page 30
2011 Microchip Technology Inc.
3.2.2
DATA SPACES
X data space is used by all instructions and supports all
Addressing modes. There are separate read and write
data buses. The X read data bus is the return data path
for all instructions that view data space as combined X
and Y address space. It is also the X address space
data path for the dual operand read instructions (MAC
class). The X write data bus is the only write path to
data space for all instructions.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restric-
tions. Bit-reversed addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedi-
cates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instruc-
tions can access the Y data address space through the
X data path as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user pro-
grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys-
ical memory, an all zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X space pointers) will return
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
3.2.3
DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data mem-
ory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws+1 for byte operations
and Ws+2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam-
ine the machine state prior to execution of the address
fault.
FIGURE 3-8:
DATA ALIGNMENT
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data
space in a MAC instruction
0x0000
W10 or W11 used to access X
data space in a MAC instruction
0x0000
15
8 7
0
0001
0003
0005
0000
0002
0004
Byte1
Byte 0
Byte3
Byte 2
Byte5
Byte 4
LSB
MSB
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