參數(shù)資料
      型號(hào): DSPIC30F4013-20I/PT
      廠商: Microchip Technology
      文件頁數(shù): 19/153頁
      文件大?。?/td> 0K
      描述: IC DSPIC MCU/DSP 48K 44TQFP
      產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
      Serial Communications using dsPIC30F I2C
      Serial Communications using dsPIC30F SPI
      Serial Communications using dsPIC30F UART
      dsPIC30F 12 bit ADC - Part 2
      dsPIC30F Addressing Modes - Part 1
      dsPIC30F Architecture - Part 1
      dsPIC30F DSP Engine & ALU
      dsPIC30F Interrupts
      dsPIC30F Motor Control PWM
      dsPIC Timers
      Asynchronous Stimulus
      dsPIC30F Addressing Modes - Part 2
      dsPIC30F Architecture - Part 2
      dsPIC30F 12-bit ADC Part 1
      標(biāo)準(zhǔn)包裝: 160
      系列: dsPIC™ 30F
      核心處理器: dsPIC
      芯體尺寸: 16-位
      速度: 20 MIPS
      連通性: CAN,I²C,SPI,UART/USART
      外圍設(shè)備: AC'97,欠壓檢測(cè)/復(fù)位,I²S,POR,PWM,WDT
      輸入/輸出數(shù): 30
      程序存儲(chǔ)器容量: 48KB(16K x 24)
      程序存儲(chǔ)器類型: 閃存
      EEPROM 大小: 1K x 8
      RAM 容量: 2K x 8
      電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
      數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
      振蕩器型: 內(nèi)部
      工作溫度: -40°C ~ 85°C
      封裝/外殼: 44-TQFP
      包裝: 托盤
      配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
      AC164305-ND - MODULE SKT FOR PM3 44TQFP
      其它名稱: DSPIC30F401320IPT
      2010 Microchip Technology Inc.
      DS70138G-page 115
      dsPIC30F3014/4013
      Receive Error Interrupts:
      A receive error interrupt is indicated by the ERRIF
      bit. This bit shows that an error condition
      occurred. The source of the error can be deter-
      mined by checking the bits in the CAN Interrupt
      register, CiINTF.
      - Invalid Message Received:
      If any type of error occurred during reception of
      the last message, an error is indicated by the
      IVRIF bit.
      - Receiver Overrun:
      The RXnOVR bit indicates that an overrun
      condition occurred.
      - Receiver Warning:
      The RXWAR bit indicates that the Receive Error
      Counter (RERRCNT<7:0>) has reached the
      warning limit of 96.
      - Receiver Error Passive:
      The RXEP bit indicates that the Receive Error
      Counter has exceeded the error passive limit of
      127 and the module has gone into error passive
      state.
      17.5
      Message Transmission
      17.5.1
      TRANSMIT BUFFERS
      The CAN module has three transmit buffers. Each of
      the three buffers occupies 14 bytes of data. Eight of the
      bytes are the maximum 8 bytes of the transmitted mes-
      sage. Five bytes hold the standard and extended
      identifiers and other message arbitration information.
      17.5.2
      TRANSMIT MESSAGE PRIORITY
      Transmit priority is a prioritization within each node of
      the pending transmittable messages. There are
      4 levels
      of
      transmit
      priority.
      If
      TXPRI<1:0>
      (CiTXnCON<1:0>, where n = 0, 1 or 2, represents a
      particular transmit buffer) for a particular message buf-
      fer is set to ‘11’, that buffer has the highest priority. If
      TXPRI<1:0> for a particular message buffer is set to
      ‘10’ or ‘01’, that buffer has an intermediate priority. If
      TXPRI<1:0> for a particular message buffer is ‘00’, that
      buffer has the lowest priority.
      17.5.3
      TRANSMISSION SEQUENCE
      To initiate transmission of the message, the TXREQ bit
      (CiTXnCON<3>) must be set. The CAN bus module
      resolves any timing conflicts between setting of the
      TXREQ bit and the Start-of-Frame (SOF), ensuring that if
      the priority was changed, it is resolved correctly before the
      SOF occurs. When TXREQ is set, the TXABT
      (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR
      (CiTXnCON<4>) flag bits are automatically cleared.
      Setting TXREQ bit simply flags a message buffer as
      enqueued for transmission. When the module detects
      an available bus, it begins transmitting the message
      which has been determined to have the highest priority.
      If the transmission completes successfully on the first
      attempt, the TXREQ bit is cleared automatically and an
      interrupt is generated if TX1IE was set.
      If the message transmission fails, one of the error
      condition flags is set, and the TXREQ bit remains set,
      indicating that the message is still pending for transmis-
      sion. If the message encountered an error condition
      during the transmission attempt, the TXERR bit is set,
      and the error condition may cause an interrupt. If the
      message loses arbitration during the transmission
      attempt, the TXLARB bit is set. No interrupt is
      generated to signal the loss of arbitration.
      17.5.4
      ABORTING MESSAGE
      TRANSMISSION
      The system can also abort a message by clearing the
      TXREQ bit associated with each message buffer.
      Setting the ABAT bit (CiCTRL<12>) requests an abort
      of all pending messages. If the message has not yet
      started transmission, or if the message started but is
      interrupted by loss of arbitration or an error, the abort is
      processed. The abort is indicated when the module
      sets the TXABT bit and the TXnIF flag is not
      automatically set.
      17.5.5
      TRANSMISSION ERRORS
      The CAN module detects the following transmission
      errors:
      Acknowledge error
      Form error
      Bit error
      These transmission errors do not necessarily generate
      an interrupt but are indicated by the transmission error
      counter. However, each of these errors causes the
      transmission error counter to be incremented by one.
      Once the value of the error counter exceeds the value
      of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
      (CiINTF<10>) are set. Once the value of the error
      counter exceeds the value of 96, an interrupt is
      generated and the TXWAR bit in the Error Flag register
      is set.
      相關(guān)PDF資料
      PDF描述
      DSPIC30F4013-30I/PT IC DSPIC MCU/DSP 48K 44TQFP
      516-090-000-421 CONN RCPT 90POS RACK & PANEL
      516-090-000-411 CONN RCPT 90POS RACK & PANEL
      516-038-000-251 CONN RCPT 38POS RACK & PANEL
      AT89C51RC2-RLRUL MCU 8051 32K FLASH 3V 44-VQFP
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      DSPIC30F4013-30I/ML 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC General Purpose RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
      DSPIC30F4013-30I/P 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC General Purpose RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
      DSPIC30F4013-30I/P 制造商:Microchip Technology Inc 功能描述:16BIT MCU-DSP 30MHZ 30F4013 DIP40
      DSPIC30F4013-30I/PT 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC General Purpose RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
      DSPIC30F4013-30I/PT 制造商:Microchip Technology Inc 功能描述:DIGITAL SIGNAL CONTROLLER 16 BIT ((NW))