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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DSPIC30F3014-30I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 147/153闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DSPIC MCU/DSP 24K 44QFN |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 妯欐簴鍖呰锛� | 45 |
| 绯诲垪锛� | dsPIC™ 30F |
| 鏍稿績铏曠悊鍣細 | dsPIC |
| 鑺珨灏哄锛� | 16-浣� |
| 閫熷害锛� | 30 MIP |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 30 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 24KB锛�8K x 24锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 1K x 8 |
| RAM 瀹归噺锛� | 2K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.5 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x12b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-VQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 651 (CN2011-ZH PDF) |
| 閰嶇敤锛� | XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 鍏跺畠鍚嶇ū锛� | DSPIC30F301430IML |
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2010 Microchip Technology Inc.
DS70138G-page 93
dsPIC30F3014/4013
14.2
I2C Module Addresses
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is 鈥�0鈥�, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 LSbs of the
I2CADD register.
If the A10M bit is 鈥�1鈥�, the address is assumed to be a
10-bit address. When an address is received, it is com-
pared with the binary value, 鈥�11110 A9 A8鈥� (where A9
and A8 are two Most Significant bits of I2CADD). If that
value matches, the next address is compared with the
Least Significant 8 bits of I2CADD, as specified in the
10-bit addressing protocol.
14.3
I2C 7-Bit Slave Mode Operation
Once enabled (I2CEN = 1), the slave module waits for
a Start bit to occur (i.e., the I2C module is 鈥業dle鈥�). Follow-
ing the detection of a Start bit, 8 bits are shifted into
I2CRSR, and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the
rising edge of SCL.
If an address match occurs, an Acknowledgement is
sent and the Slave Event Interrupt Flag (SI2CIF) is set
on the falling edge of the ninth (ACK) bit. The address
match does not affect the contents of the I2CRCV buf-
fer or the RBF bit.
14.3.1
SLAVE TRANSMISSION
If the R_W bit received is a 鈥�1鈥�, the serial port goes into
Transmit mode. It sends an ACK on the ninth bit and
then holds SCL to 鈥�0鈥� until the CPU responds by writing
to I2CTRN. SCL is released by setting the SCLREL bit,
and 8 bits of data are shifted out. Data bits are shifted
out on the falling edge of SCL, such that SDA is valid
during SCL high. The interrupt pulse is sent on the
falling edge of the ninth clock pulse, regardless of the
status of the ACK received from the master.
14.3.2
SLAVE RECEPTION
If the R_W bit received is a 鈥�0鈥� during an address
match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), then
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
14.4
I2C 10-Bit Slave Mode Operation
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
addressed for a write operation with two address bytes
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
messages, but the bits being compared are different.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal 鈥�11110鈥� (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit is cleared to indi-
cate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.
The low byte of the address is then received and com-
pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
14.4.1
10-BIT MODE SLAVE TRANSMISSION
Once a slave is addressed in this fashion with the full
10-bit
address
(we
refer
to
this
state
as
鈥淧RIOR_ADDR_MATCH鈥�), the master can begin
sending data bytes for a slave reception operation.
TABLE 14-1:
7-BIT I2C SLAVE
ADDRESSES SUPPORTED BY
dsPIC30F
0x00
General Call Address or Start Byte
0x01-0x03
Reserved
0x04-0x07
HS mode Master Codes
0x08-0x77
Valid 7-Bit Addresses
0x78-0x7b
Valid 10-Bit Addresses (lower 7 bits)
0x7c-0x7f
Reserved
Note:
The I2CRCV is loaded if the I2COV bit = 1
and the RBF flag = 0. In this case, a read
of the I2CRCV was performed but the
user did not clear the state of the I2COV
bit before the next receive occurred. The
acknowledgement is not sent (ACK = 1)
and the I2CRCV is updated.
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