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| 型號： | DSPIC30F2011-30I/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 15/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 12K 18DIP |
| 產(chǎn)品培訓(xùn)模塊： | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | dsPIC™ 30F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 30 MIP |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 12KB（4K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 650 (CN2011-ZH PDF) |
| 配用： | AC30F005-ND - MODULE SCKT DSPIC30F 18DIP/SOIC DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE ACICE0202-ND - ADAPTER MPLABICE 18P 300 MIL |
| 其它名稱： | DSPIC30F2011-30IP |
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dsPIC30F Flash Programming Specification
DS70102K-page 22
2010 Microchip Technology Inc.
clocked out. The programmer can begin to clock out
the response 20
μsec after PGD is brought low, and it
must provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
Once the entire response is clocked out, the
programmer should terminate the clock on PGC until it
is time to send another command to the programming
executive. This protocol is illustrated in Figure 7-2.
7.3
SPI Rate
In Enhanced ICSP mode, the dsPIC30F operates from
the fast internal RC oscillator, which has a nominal
frequency of 7.37 MHz. This oscillator frequency yields
an effective system clock frequency of 1.84 MHz. Since
the SPI module operates in Slave mode, the
programmer must limit the SPI clock rate to a
frequency no greater than 1 MHz.
Note:
If the programmer provides the SPI with a
clock faster than 1 MHz, the behavior of
the programming executive will be
unpredictable.
7.4
Time Outs
The programming executive uses no Watchdog Timer
or time out for transmitting responses to the
programmer. If the programmer does not follow the flow
control mechanism using PGC, as described in
col”, it is possible that the programming executive will
behave unexpectedly while trying to send a response
to the programmer. Since the programming executive
has no time out, it is imperative that the programmer
correctly follow the described communication protocol.
As a safety measure, the programmer should use the
command time outs identified in Table 8-1. If the
command time out expires, the programmer should
reset
the
programming
executive
and
start
programming the device again.
FIGURE 7-2:
PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
1
2
15 16
1
2
15 16
PGC
PGD
PGC = Input
PGC = Input (Idle)
Host Transmits
Last Command Word
PGD = Input
PGD = Output
P8
1
2
15 16
MSB X X X LSB
1
0
P9b
P10
PGC = Input
PGD = Output
P9a
Programming Executive
Processes Command
Host Clocks Out Response
P11
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